Job Title:
Senior Staff Engineer Functional Verification
About the Role:
Lead the verification of digital IP, employing System Verilog/UVM methodologies and collaborating with design teams. Provide leadership for a small, dynamic team.
Duties and Responsibilities:
* Coordinate the overall digital verification strategy in alignment with other disciplines (Concept Engineering, Analog/Mixed-Signal Design).
* Lead the digital functional verification of ASIC projects by planning, delegating, and tracking related activities.
Requirements:
* A Master's Degree in Electronic Engineering or similar.
* Fluent verbal and written communication skills in English; German as a plus.
About Our Company:
At {company} in Villach, you will shape the technologies of tomorrow and work in an international environment with more than 4+ employees. The city is located in beautiful surroundings that guarantee a high quality of life.
We are on a journey to create the best {company} for everyone. At {company}, we offer a working environment characterized by trust, openness, respect, and tolerance, and are committed to giving all applicants and employees equal opportunities.