Principal Engineer Digital Design (f/m/div)
At a glance, this is an opportunity to be at the forefront of digital innovation in Graz.
You will play a pivotal part in crafting the next generation of Battery Management System and Power Management Integrated Circuit technology.
Taking on this role, you will focus on:
* End-to-End Digital Circuit Design & Verification: Lead the entire RTL design process, from block-level to top-level, ensuring robust logic synthesis, static timing analysis, and seamless integration across clock domains
* Defining Architecture & Hardware Requirements: Translate product requirements into hardware specifications, working with system concept engineers to define optimal architectures and interfaces for digital modules
* Technical Leadership & Team Management: Plan and execute digital design activities, oversee quality inspections, provide post-silicon bring-up support, and mentor a growing team of designers and students
* DFT & Functional Safety Compliance: Lead design-for-test (DFT) efforts, including scan insertion and ATPG, while ensuring compliance with ATV ISO 26262 standards for functional safety
* Collaborate with System, Verification & Chip Integration Teams: Work closely with cross-functional teams to define hardware architectures, review verification plans, and develop test cases that achieve high coverage
* Pre-Silicon Verification & Quality Assurance: Analyze clock domain crossings (CDC) and linting, review pre-silicon verification plans, and ensure designs meet rigorous quality and testing standards
Your toolkit for success includes:
* A University degree (MSc) in Electrical Engineering, Computer Science, or a related field
* 8+ years of hands-on experience in RTL digital design, including top-level integration of complex SoCs (Analog on Top or Digital on Top)
* Strong proficiency in RTL design using Verilog and SystemVerilog
* Skilled in industry-standard tools like Excelium and Spyglass, with experience using UPF to manage power intent in design
* Competent in scripting languages such as Python, Perl, and Tcl, along with medium-level experience in behavioral modeling
* Proficient in design version control systems, including Perforce, ClearCase, SVN, and GIT
* Fluency in English is essential, and knowledge of German is a plus
Nice to have:
* Extensive experience in Digital-On-Top integration and close interaction with Digital Backend teams
* Proven track record working within Infineon's design environment and methodologies
* Proficiency in formal verification using Jasper Gold or OneSpin, with expertise in ASIL ISO 26262 functional safety standards
* Skilled in PrimeTime static timing analysis (STA), ATPG, and netlist generation
* Experience in automating design documentation processes and improving documentation flows
* Basic experience with SystemVerilog and UVM
This position requires strong communication skills and a focus on quality. We are committed to giving all applicants and employees equal opportunities.