Job Description
Job Title: Senior Staff Engineer Functional Verification
You have a passion for new technologies and are eager to contribute to our mission of creating a more sustainable future. As a Senior Staff Engineer in Functional Verification, you will lead the verification of digital IP, leveraging System Verilog/UVM methodologies, collaborating with design teams, and providing leadership for a small, dynamic team.
Key Responsibilities:
* Lead the verification of digital IP using System Verilog/UVM methodologies.
* Collaborate with design teams to ensure seamless integration.
* Provide technical leadership for a small, dynamic team.
Requirements:
* Expertise in System Verilog and UVM methodologies.
* Strong collaboration and leadership skills.
* Ability to work in a fast-paced environment.
What We Offer:
* A competitive compensation package.
* A dynamic and supportive work environment.
* Ongoing training and professional development opportunities.